1. Field of the Invention
The present invention relates to a data driving circuit, a light emitting display device using the same, and a driving method thereof, and more particularly, to a data driving circuit, a light emitting display device using the same, and a driving method thereof, from which uniform images can be displayed.
2. Discussion of Related Art
An organic light emitting display device is a flat display device that displays images using organic light emitting diode OLEDs for generating light by a recombination of electrons and holes. The organic light emitting display device has a rapid response speed and can be driven with low power consumption.
The organic light emitting display device includes a plurality of pixels located in crossing (or intersection) regions defined by data lines and scan lines. The pixels are selected when scan signals are supplied to the scan lines and are charged with voltages corresponding to data signals supplied to the data lines. The pixels generate lights with a certain (or predetermined) brightness by supplying currents corresponding to the charged voltages to organic light emitting diodes. Here, the lights with the predetermined brightness emitted from each of the pixels are summed to display images in a display region.
In addition, the organic light emitting display device includes a data driver for supplying the data signals to the data lines, and a scan driver for supplying the scan signals to the scan lines. The data driver includes at least one data driving circuit with a predetermined channel (or an output channel).
FIG. 1 is a view illustrating a conventional data driving circuit. For the convenience of description, it is assumed in FIG. 1 that the data driving circuit has j channels (or j output channels) (where j is a natural number).
Referring to FIG. 1, the conventional data driving circuit includes a shift register part 1, a sampling latch part 2, a holding latch part 3, a signal generation part 4, and an output stage 5.
The shift register part 1 is supplied with an external source start pulse SSP and an external source shift clock SSC. The shift register part 1 supplied with the source shift clock SSC and the source start pulse SSP sequentially generates j sampling signals while shifting the source start pulse SSP for every period of the source shift clock SSC. Here, the shift register part 1 includes j shift registers 11 to 1j.
The sampling latch part 2 sequentially stores data corresponding to the sampling signals sequentially supplied from the shift register part 1. Here, the sampling latch part 2 includes j sampling latches 21 to 2j to store j data.
The holding latch part 3 is inputted with and stores data from the sampling latch part 2. The holding latch part 3 supplies its stored data to the signal generator part 4. Here, the holding latch part 3 includes j holding latches 31 to 3j.
The signal generation part 4 is inputted with data (or digital data) supplied from the holding latch part 3 and then generates j data signals (or j analog data signals) corresponding to the inputted data. Here, the signal generator 4 includes j digital-analog converters (hereinafter, referred to as “DAC”) 41 to 4j. That is, the signal generator 4 generates j data signals using the DACs 41 to 4j located in each of the channels, and supplies the generated data signals to the output stage 5.
The output stage 5 supplies j data signals supplied from the signal generator 4 to j data lines D1 to Dj, respectively. Then, the data signals are supplied to the pixels, displaying predetermined images.
However, the conventional data driving circuit has a problem in that uniform data signals cannot be generated due to a variation of DACs 41 to 4j located in each of the channels. In practice, although the process procedure for manufacturing the DACs 41 to 4j is controlled precisely during the manufacturing of the DACs 41 to 4j, the DACs 41 to 4j still have a variation of about +3 mV between their outputs. Therefore, although data with the same gray level value is inputted to each of the DACs 41 to 4j, data with different voltage values (or current values) are generated. As such, if the data signals with different voltage values (or current values) are generated when the same gray level values are inputted to each of the DACs 41 to 4j, then the light emitting display device displays non-uniform images. In particular, if the DACs 41 to 4j with a certain amount of the variation are arranged adjacent to one another, then stripe-type noises can be added to the images.